1. Field of the Invention
The present invention relates to an A-D converter, and more particularly, it relates to an A-D converter of a sequential comparison system formed on a semiconductor integrated circuit, which employs a plurality of serially connected MOS capacitors for detecting the voltage of an analog signal.
2. Description of the Background Art
A-D converters for converting analog signals to digital signals are provided in various systems. For example, Japanese Patent Laying-Open Gazette No. 5-29941 (1993) discloses an invention related to a parallel-serial converter, and Japanese Patent Laying-Open Gazette No. 9-83316 (1997) discloses an A-D converter of a two-step parallel system. The present invention relates to an A-D converter of a sequential comparison system. For example, Japanese Patent Laying-Open Gazettes Nos. 2-246621 (1990), 5-235767 (1993) and 6-53834 (1994) disclose A-D converters of the sequential comparison system
Among the inventions disclosed in these gazettes, the invention described in Japanese Patent Laying-Open Gazette No. 6-53834 has been proposed in order to reduce nonlinear errors in the A-D converter, and has the same object as that of the present invention. However, although the A-D converter disclosed in Japanese Patent Laying-Open Gazette No. 6-53834 and the A-D converter according to the present invention are identical in system to each other, the circuit structures thereof are remarkably different from each other, and hence the A-D converter described in the above gazette is not employed for describing problems of the prior art. On the other hand, Japanese Patent Laying-Open Gazette No. 54-153560 (1979) discloses means for correcting errors caused in steps of fabricating an A-D converter.
FIG. 16 is a circuit diagram showing an exemplary structure of a conventional A-D converter 1. The A-D converter 1 shown in FIG. 16 is remarkably different in circuit structure from the A-D converters described in all aforementioned gazettes.
The A-D converter 1 is formed by a voltage generating circuit 2 for generating a plurality of reference voltages, a compare circuit 3 for comparing the level of an analog signal VIN with a level generated from first and second reference voltages, for example, and a sequential approximate register SAR for storing data for controlling the reference voltages outputted from the voltage generating circuit 2.
The voltage generating circuit 2 includes a resistive ladder network 4 for evenly dividing a ground voltage GND and a reference voltage VREF and generating reference voltages (tap voltages) VT0 to VT15. Namely, resistances R0 to R15 having the same resistance values are serially connected with each other, to form the resistive ladder network 4. The compare circuit 3, which is a chopper circuit, is formed by a MOS capacitor C1 having first and second electrodes, a MOS capacitor C2 having first and second electrodes and connecting the second electrode to that of the MOS capacitor C1, switches S-pre1, S-pre2, S-cmp1, S-cmp2 and S-chop, and a CMOS inverter 5 having input and output terminals and connecting the input terminal to a node N1 between the MOS capacitors C1 and C2. The MOS capacitors C1 and C2 are serially connected with each other to form a single series-connected body 6. The analog signal VIN and the first reference voltage are applied to a first end (the first electrode of the MOS capacitor C1) of the series-connected body 6 through the switches S-pre1 and S-cmp1 respectively. A first switch group 7 selects the first reference voltage from the plurality of reference voltages generated by the voltage generating circuit 2. On the other hand, the ground voltage GND and the second reference voltage are applied to a second end (the first electrode of the MOS capacitor C2 ) of the series-connected body 6 through the switches S-pre2 and S-cmp2 respectively. A second switch group 8 selects the second reference voltage from the plurality of reference voltages generated by the voltage generating circuit 2.
The A-D converter 1 has resolution of six bits, so that four bits relate to the structure of the resistive ladder network 4 and the remaining two bits relate to the structures of the MOS capacitors C1 and C2.
In order to simplify the illustration, an offset adjusting circuit is omitted from the circuit diagram of the A-D converter 1.
The A-D converter 1 decides the values of the bits B5 to B0 successively from the most significant bit B5 by sequential comparison. The A-D converter 1 decides whether the most significant bit B5 is "1" or "0" through comparison as to whether the voltage of the analog signal VIN is larger or smaller than half the reference voltage VREF. Throughout the specification, it is assumed that numerals with "" marks are binary numbers. Then, the A-D converter 1 decides the value of the bit B4 which is lower than the most significant bit B5 by one order, and decides the values of the remaining bits B3 to B0 in descending order In order to perform such sequential comparison, the A-D converter 1 first closes a switch S1-8 in the first switch group 7 while closing a switch S2-0 in the second switch group 8, and then successively closes the remaining switches to change the voltages by half preceding voltage change. Namely, the A-D converter 1 closes a switch S1-4 or S1-12 following the switch S1-8, then a switch S1-2, S1-6, S1-10 or S1-14, and then a switch S1-1, S1-3, S1-5, S1-7, S1-9, S1-11, S1-13 or S1-15. When settling a finally selected switch of the first switch group 7, the A-D converter 1 stops the switch selecting operation for the first switch group 7 and performs a selecting operation for the second switch group 8. The A-D converter 1 first closes a switch S2-2, and then a switch S2-1 or S2-3.
A detection circuit 9 performs comparison in stages of deciding the respective bits B5 to B0. The detection circuit 9 compares the voltage of the node N1 between the MOS capacitors C1 and C2 in application of the analog signal VIN with reference to the voltage GND to the MOS capacitors C1 and C2 with the voltage of the node N1 in application of the voltage generated in the resistive ladder network 4 to the MOS capacitors C1 and C2. In this comparison, the detection circuit 9 first closes the switch S-chop and precharges the voltage of the threshold voltage. The threshold voltage, which is employed as the reference for the detection to be compared with a voltage applied to the input terminal by the detection circuit 9, coincides with a precharge voltage. FIG. 17 is a graph showing the relation between the threshold voltage and input and output voltages of the CMOS inverter 5. Referring to FIG. 17, power supply voltages supplied to the CMOS inverter 5 are 0 V and VDD, and the threshold voltage of the CMOS inverter 5 is 0.5VDD. In precharging, the analog signal VIN and the ground voltage GND are applied to the first electrodes of the MOS capacitors C1 and C2 respectively.
Following completion of the precharging, the compare circuit 3 opens the switch S-chop and increases the input impedance thereby bringing the node N1 between the MOS capacitors C1 and C2 into a floating state, and compares the voltage of the node N1 with a threshold voltage VTH1. At this time, any two of the reference voltages VT0 to VT15 generated in the resistive ladder network 4 are applied to the first electrodes of the MOS capacitors C1 and C2 as the first and second reference voltages respectively.
With reference to FIG. 18, the operation of the A-D converter 1 is now described in association with operations of the switches S-pre1, S-pre2, S-cmp1, S-cmp2 and S-chop of the compare circuit 3 and the switches S1-0 to S1-15 and S2-0 to S2-3 of the voltage generating circuit 2. FIG. 18 is a timing chart for illustrating the operation of the conventional A-D converter 1.
The A-D converter 1 closes the switch S-chop of the compare circuit 3 at a time t1. At the same time, the A-D converter 1 closes the switches S-pre1 and S-pre2 and opens the switches S-cmp1 and S-cmp2. In this state, charges are supplied through the switch S-chop for maintaining the voltage of the node N1 between the MOS capacitors C1 and C2 at the threshold voltage VTH1 of the compare circuit 3 (the detection circuit 9). The threshold voltage VTH1, which is the threshold voltage of the CMOS inverter 5 formed by transistors TR1 and TR2, serves as a precharge voltage in precharging. A voltage corresponding to the difference between the voltage of the analog signal VIN and the threshold voltage VTH1 is applied to the MOS capacitor C1. On the other hand, a voltage corresponding to the difference between the threshold voltage VTH1 and the voltage GND is applied to the MOS capacitor C2.
At a time t2, the A-D converter 1 opens the switch S-chop. The CMOS inverter 5 has a high input impedance, i.e., the node N1 is in a floating state, thereby maintaining the voltage of the node N1. Between the time t2 and a time t3 the A-D converter 1 opens the switches S-pre1 and S-pre2 while simultaneously closing the switch S-cmp1 and S-cmp2. The A-D converter 1 selectively closes the switch S1-0 to S1-15 and S2-0 to S2-3 in the first and second switch groups 7 and 8 of the voltage generating circuit 2 in accordance with the data of the sequential approximate register SAR, in relation shown in Tables 1 and 2 with the data of the sequential approximate register SAR.
TABLE 1 ______________________________________ B5 B4 B3 B2 closed switch ______________________________________ 0 0 0 0 S1-0 0 0 0 1 S1-1 0 0 1 0 S1-2 0 0 1 1 S1-3 0 1 0 0 S1-4 0 1 0 1 S1-5 0 1 1 0 S1-6 0 1 1 1 S1-7 1 0 0 0 S1-8 1 0 0 1 S1-9 1 0 1 0 S1-10 1 0 1 1 S1-11 1 1 0 0 S1-12 1 1 0 1 S1-13 1 1 1 0 S1-14 1 1 1 1 S1-15 ______________________________________
TABLE 2 ______________________________________ B1 B0 closed switch ______________________________________ 0 0 S2-0, S3-0 0 1 S2-1, S3-1 1 0 S2-2, S3-2 1 1 S2-3, S3-3 ______________________________________
Between the times t1 to t3, the sequential approximate register SAR stores data having a value "100000". During the times t1 to t3, therefore, the switches S1-8 and S2-0 are closed. The compare circuit 3 makes comparison while the switches S-cmp1 and S-cmp2 are closed. The A-D converter 1 settles the value of the most significant bit B5 of an outputted digital signal at "1" if the voltage of the node N1 between the MOS capacitors C1 and C2 is higher than the threshold voltage VTH1, otherwise at "0".
In comparison made between the time t3 and a time t5, data of the sequential approximate register SAR is "110000" if the value of the most significant bit B5 of the digital signal is "1", or the data is "010000" if the value is "0". During the times t3 to t5, the switch S1-12 is closed if the data of the sequential approximate register SAR is "110000", or the switch S1-4 is closed if the data is "01000" for comparison. The A-D converter 1 continues such sequential comparison, for successively deciding the values of the respective bits B5 to B0 of the digital signal in descending order.
In the sequential comparison, the voltage VN1 of the node N1 between the MOS capacitors C1 and C2 is expressed as follows: ##EQU1## where [:] is a symbol forming a decimal value from binary data. For example, [B5:B2] indicates decimal expression of a value expressed in four digits consisting of the bits B5 to B2 of the sequential approximate register SAR. Further, [B1:B0] indicates decimal expression of a value expressed in two digits consisting of the bits B1 and B0 of the sequential approximate register SAR. When the sequential approximate register SAR stores data "110010", for example, [B5:B2] expresses 12 and [B1:B0] expresses 2. Assuming that the capacity of the MOS capacitor C1 is four times that of the MOS capacitor C2, application of the condition C1=C2.times.4 to the above expression 1 leads to the following expression 2: ##EQU2##
The compare circuit 3 outputs "1" when the voltage VN1 of the node N1 is lower than the threshold voltage VTH1, i.e., the condition described in the following expression 3 is satisfied: ##EQU3##
The following relation holds between the analog signal VIN inputted in the A-D converter 1 and a voltage expressed by a digital signal OUT outputted from the A-D converter 1. The A-D converter 1 decides the digital signal OUT at the maximum value satisfying the relation of the following expression 4: ##EQU4##
In other words, the analog signal VIN is within the range of the following expression 5, when the sequential approximate register SAR obtains specific data ##EQU5##
The relations in the above expressions 1 to 5 hold when the elements, such as resistances and capacitances, for example, of the A-D converter 1 shown in FIG. 16 have ideal characteristics. In reality, however, the elements of the A-D converter 1 not necessarily have ideal characteristics. Particularly when the A-D converter 1 is to be implemented on a semiconductor integrated circuit, the series-connected body 6 frequently utilizes the MOS capacitors C1 and C2. Each of the MOS capacitors C1 and C2, which is in a structure shown in FIG. 19, for example, has a capacitance-bias voltage characteristic shown in FIG 20, for example. FIG. 19 is a model diagram showing the sectional structure of each MOS capacitor employed in the conventional A-D converter 1. FIG. 20 is a graph showing the relation between a gate electrode voltage (horizontal axis) with reference to the potential of a diffusion layer and the capacitance (vertical axis) of each MOS capacitor. Referring to FIG. 19, a gate electrode 10 and a diffusion layer 12 are formed through a gate oxide film 11, so that the MOS capacitor has a capacitance between the gate electrode 10 and the diffusion layer 12. The remaining elements of the A-D converter 1 are also formed on a silicon substrate 13 serving as the base for forming the gate electrode 10, the gate oxide film 11 and the diffusion layer 12.
When the structure shown in FIG. 19 is applied to each of the MOS capacitors C1 and C2 shown in FIG. 16, the gate electrode 10 is connected to the input terminal (gate electrodes of the transistors TR1 and TR2) of the CMOS inverter 5, in order to avoid a bad influence from a parasitic capacitance. When the analog signal VIN is at a high voltage and hence any switch (e.g., S1-15) of the first switch group 7 closer to the terminal receiving the reference voltage VREF conducts, the potential of the diffusion layer 12 of the MOS capacitor C1 becomes higher than that of the gate electrode 10 and the capacitance of the MOS capacitor C1 is less than four times that of the MOS capacitor C2. When [B1:B0] is nonzero, therefore, the A-D converter 1 causes an error in A-D conversion. Thus, the relation shown in the following expression 6 takes place between the voltage indicated by the digital signal [B5:B0] obtained in the sequential approximate register SAR and the analog signal VIN: ##EQU6##
where .DELTA.V1 and .DELTA.V2 represent errors caused in [B5:B0] +1 and [B5:B0] respectively, which are maximized when [B5:B0] +1 and [B5:B0] are 4n+3 respectively (n=9-15) and minimized when these values are zero.
While the A-D converter 1 closes any switch of the first switch group 7, the errors resulting from capacitance change of the MOS capacitor C1 are increased as the voltage selected in accordance with the closed switch is closer to the reference voltage VREF. FIG. 21 is a graph showing the result of the above expression 6, i.e., the error characteristic of A-D conversion, and illustrates the relation between the values of the digital signal and the errors.
In order to suppress the errors resulting from capacitance change of the MOS capacitor C1, bias voltage dependence of the MOS capacitor C1 may be reduced. For this purpose, the impurity concentration of the diffusion layer 12 of the MOS capacitor C1 is increased in general. In case of injecting an impurity with an injector, however, it is necessary to inject the impurity over a long time if the injection rate per unit time cannot be increased, leading to reduction of producibility.
In the conventional A-D converter having the aforementioned structure, the capacitance of each MOS capacitor varies with the voltage applied across its electrodes, to disadvantageously cause errors in the values shown by the analog and digital signals.